The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application No. 2001-22372, filed on Apr. 25, 2001, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method of forming shallow trench isolation and a method of manufacturing a semiconductor memory device using the same.
2. Description of Related Art
A shallow trench isolation (STI) serves as an isolation region to prevent a short circuit between two adjacent devices, such as transistors. A STI is formed such that a shallow trench is formed in a semiconductor substrate by anisotropic etching using a silicon nitride layer as a hard mask, and the shallow trench is then filled with an insulating layer.
The STI has different characteristics depending on whether it has a liner layer or not. In the case of the STI having no liner layer, there is a problem in that defects such as a shallow pits occur due to a subsequent oxidation. The defects deteriorate electrical characteristics of the corresponding devices, and may cause a leakage current in a junction region (e.g., p-n junction region) thereof, thereby affecting isolation of the device.
In an effort to solve these problems, a technique of forming the STI as including a liner layer has been developed. FIGS. 1A to 1F are cross-sectional views illustrating such a process of forming a conventional STI.
Referring to FIG. 1A, a semiconductor substrate 10 having a pad oxide layer 11 and a mask layer 12 formed thereon is provided. The semiconductor substrate 10 is made of silicon and has a field region 10-1 and active regions 10-2. The mask layer 12 is made of a nitride. The substrate 10 and the pad oxide layer 11 are patterned using the mask layer 12 to form a shallow trench 13 in the field region 10-1 of the substrate 10.
Referring to FIG. 1B, a buffer oxide layer 14 is formed in the shallow trench 13, and then a liner layer 15 is formed to cover the buffer oxide layer 14. The buffer oxide layer 14 is formed by growing a thermal oxide layer on side portions and a bottom portion of the shallow trench 13, in order to cure any damage that may have occurred during an etching process of the semiconductor substrate 10 for forming the trench 13 and to prevent stress and/or a trap center from developing between the liner layer 15 and the silicon substrate 10. The liner layer is generally made of a nitride.
Subsequently, as shown in FIG. 1C, the shallow trench 13 is filled with an insulating layer 16. Thereafter, as shown in FIG. 1D, the liner layer 15 and the insulating layer 16 formed on the mask layer 12 are polished by a CMP process so as to planarize a surface of the substrate 10, so that the mask layer 12 of a predetermined thickness remains.
Next, as shown in FIG. 1E, the mask layer 12 is removed. Finally, as shown in FIG. 1F, a wet-etching process is performed to remove the pad oxide layer 11. As a result, a completed shallow trench isolation (STI) 17 is formed.
The STI 17 as described above can prevent defects from occurring due to subsequent oxidation. However, this conventional method of forming the STI has a problem in that when the mask layer 12 is removed, as shown in FIG. 1E, portions of the liner layer 15 within the shallow trench 13 are also removed, thereby forming dents 18. In addition, as shown in FIG. 1F, due to the subsequent wet-etching process used to remove the pad oxide layer 11, dents 18 become deeper and broader. As a result, an electric field concentration occurs and a transistor hump is formed.
FIG. 2 is a photograph of the STI fabricated according to a conventional method such as described above. As can be seen in FIG. 2, a very deep dent 28 is formed at the top corner of shallow trench 23, i.e., both ends of the active region 10-2 of FIG. 1. In FIG. 2, liner layer 25 is illustrated as formed in the trench 23. Additionally, due to stress occurring during a subsequent thermal oxidation process to form a gate oxide layer, a portion of the gate oxide layer on the top corner portion of the shallow trench 23 is formed as being thinner than that on the active region 20-2. That is, a thinning of the gate oxide layer occurs.
FIGS. 3A to 3F are cross-sectional views illustrating a conventional process of forming the STI, which prevents formation of dents. Referring to FIG. 3A, a semiconductor substrate 30 having a pad oxide layer 31 and a mask layer 32 formed thereon is provided. The semiconductor substrate 30 is made of silicon and has a field region 30-1 and active regions 30-2. The mask layer 32 is made of a nitride. The substrate 30 and the pad oxide layer 31 are patterned using the mask layer 32 to form a shallow trench 33 in the field region 30-1 of the substrate 30.
Referring to FIG. 3B, a buffer oxide layer 34 is formed to cover the shallow trench 33. The mask layer 32 is isotropically etched to expose a portion of the buffer oxide layer 34 on a top corner of the shallow trench 33. Thereafter, as shown in FIG. 3C, a liner layer 35 is formed over the whole surface of the substrate 30. The shallow trench 33 is filled with an insulating layer 36 and the liner layer 35 is generally made of a nitride.
Subsequently, as shown in FIG. 3D, the liner layer 35 and the insulating layer 36 formed on the mask layer 32 are polished by a CMP process so as to planarize a surface of the substrate 30, so that the mask layer 32 and the liner layer 35 of a predetermined thickness remain.
Referring to FIG. 3E, the remaining mask layer 32 and liner layer 35 are removed. Referring to FIG. 3F, the pad oxide layer 31 remaining on the active regions 30-2 of the substrate 30 are removed by a wet-etching technique, and the structure is planarized, whereby a STI isolation 37 is completed.
However, even though the occurrence of a dent is prevented in the above noted conventional fabrication method, the STI of FIG. 3F has the following problem. Due to stress of the mask layer 32 formed on the active regions 30-2 of the substrate 30, there is a tendency that a lesser amount of buffer oxide layer 34 than desired grows at a top corner of the shallow trench 33. In order to overcome this stress and grow a sufficient amount of buffer oxide layer 34 at the top corner of the shallow trench 33, the buffer oxide layer 34 has to be formed thicker than otherwise necessary. However, when the buffer oxide layer 34 is formed thicker, there occurs a problem in that a junction leakage current increases.
With further regard to the conventional fabrication methods, a cleaning process is generally performed before a process to form the gate oxide layer. The buffer oxide layer 34 is exhausted during the cleaning process to cause a dent. Also, when the gate oxide layer is formed in a subsequent process, the gate oxide layer becomes thinner at the top corner of the shallow trench than at other portions thereof. That is, a thinning of the gate oxide layer occurs. Such a thinning of the gate oxide layer becomes deeper in the case of a dual gate oxide layer. This is described below with reference to FIGS. 4A to 4E.
FIGS. 4A to 4E are cross-sectional views illustrating a conventional process of forming a gate oxide layer, subsequent to the structure as formed in FIG. 3F. Referring to FIG. 4A, the STI 45 includes a shallow trench 41 formed in the field region 40-1 of a substrate 40. A buffer oxide layer 42, a liner layer 43 and an insulating layer 44 are formed in the shallow trench 41. The substrate 40 further includes first and second active regions 40-21 and 40-22. A relatively thick gate oxide layer is to be formed on the first active region 40-21, and a relatively thin gate oxide layer is to be formed on the second active region 40-22.
Referring to FIG. 4B, a cleaning process is performed. The buffer oxide layer 42 is exhausted during the cleaning process, so that dents 45a occur at the top corners of the shallow trench 41.
Referring to FIG. 4C, a relatively thick first gate oxide layer 46 is formed on the whole surface of the substrate 40 other than the STI 45, as having a thickness TOX11. A portion of the first gate oxide layer 46 on the top corners of the shallow trench 41 in which the dents 45a occurs has a thickness TOX12, which is thinner than the other portion thereof.
Referring to FIG. 4D, a wet-etching process is performed to remove a portion of the first gate oxide layer 46 formed on the second active region 40-22. The dent 45a is deepened by the wet-etching process. At this point, the thicker that first gate oxide layer 46 is, the deeper dent 45a becomes.
Referring to FIG. 4E, a relatively thin second oxide layer 47 is formed on the second active region 40-22 of the substrate 40, as having thickness TOX21.
Accordingly, a portion of the second gate oxide layer 47 on the top corner of the shallow trench 41 in which the dent 45a occurs, has a thickness TOX22 thinner than other portions thereof. As described above, in a semiconductor device having such a conventional STI, a thinning of the gate oxide layer as well as formation of dents occur, whereupon the gate oxide layer is non-uniformly formed. A gate oxide layer having a non-uniform thickness lowers a breakdown voltage, so that a parasitic current occurs in a transistor, thereby deteriorating characteristics of the device.
The present invention is therefore directed to a method of forming shallow trench isolation and a method of manufacturing a semiconductor device using the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
To overcome the above noted and other problems, a method of forming a semiconductor device having a shallow trench isolation (STI) which can prevent occurrence of dents and insufficient, non-uniform growth of a gate oxide layer, is provided.
It is another object of the present invention to provide a method of forming a semiconductor device having a STI, whereby the semiconductor device has excellent device characteristics.
In order to achieve the above noted objects, an embodiment of the present invention provides a method of forming a shallow trench isolation of a semiconductor device, including: a) providing a semiconductor substrate including a field region and an active region; b) forming a first insulating layer and a mask layer on the active region that expose the field region of the substrate; c) etching the exposed field region of the substrate to form a shallow trench; d) etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the shallow trench; e) forming a second insulating layer in the shallow trench, the second insulating layer having a step higher than the active region; f) forming a liner layer as covering the mask layer and the second insulating layer within the shallow trench; g) forming a third insulating layer as covering the liner layer and filling the shallow trench; h) etching the mask layer, the liner layer and the third insulating layer to provide a planarized surface; i) removing a remaining portion of the mask layer; and j) removing a remaining portion of the first insulating layer.
An additional object of the present invention provides a method of forming a semiconductor device, including: providing a substrate including a field region, an active region and a shallow trench isolation, the shallow trench isolation being formed in the field region of the substrate and including a first insulating layer, a liner layer on the first insulating layer, and a second insulating layer on the liner layer, the first insulating layer having a step higher than the active region of the substrate; cleaning the substate; forming a gate oxide layer on the active region of the substrate; and forming a gate on the gate oxide layer.
A further embodiment of the present invention provides a method of forming a shallow trench isolation of a semiconductor device, including: a) providing a semiconductor substrate including a field region and an active region; b) forming a first insulating layer and a mask layer that expose the field region of the substrate; c) etching the exposed field region of the substrate to form a shallow trench; d) etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the shallow trench; e) forming a second insulating layer in the shallow trench, the second insulating layer having a step higher than the active region; f) forming a liner layer as covering the mask layer and the second insulating layer within the shallow trench; g) forming a third insulating layer as covering the liner layer and filling the shallow trench; h) etching the mask layer, the liner layer and the third insulating layer to provide a planarized surface; i) removing a remaining portion of the mask layer; j) removing a remaining portion of the first insulating layer; k) cleaning the substrate; and l) forming a gate oxide layer on the active region of the substrate.
A still further embodiment of the present invention provides a method of forming a semiconductor device, including: providing a substrate including a field region, first and second active regions and a shallow trench isolation, the shallow trench isolation being formed in the field region of the substrate and including a first insulating layer, a liner layer on the first insulating layer, and a second insulating layer on the liner layer, the first insulating layer having a step higher than the first and second active regions of the substrate; cleaning the substate; forming a first gate oxide layer over an entire surface of the substrate; etching the first gate oxide layer so that the first gate oxide layer remains on the first active region of the substrate; and forming a second gate oxide layer on the second active region of the substrate.
An additional further embodiment of the present invention provides a method of forming a semiconductor device, including: a) providing a semiconductor substrate including a field region and first and second active regions; b) forming a first insulating layer and a mask layer on the substrate that expose the field region of the substrate; c) etching the exposed field region of the substrate to form a shallow trench; d) etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the shallow trench; e) forming a second insulating layer in the shallow trench, the second insulating layer having a step higher than the first and second active regions; f) forming a liner layer as covering the mask layer and the second insulating layer within the shallow trench; g) forming a third insulating layer as covering the liner layer and filling the shallow trench; h) etching the mask layer, the liner layer and the third insulating layer to provide a planarized surface; i) removing a remaining portion of the mask layer; j) removing a remaining portion of the first insulating layer; k) cleaning the substate; l) forming a first gate oxide layer over an entire surface of the substrate; m) etching the first gate oxide layer so that the first gate oxide layer remains on the first active region of the substrate; and n) forming a second gate oxide layer on the second active region of the substrate.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.